1. Field of the Invention
This invention relates to a manufacturing method of a junction field effect transistor and, more particularly, to a manufacturing method of a junction field effect transistor suitable for use in amplification of a high-frequency signal.
2. Description of the Related Art
Mobile transmission terminals rapidly being popularized in recent years use waves of frequency bands as high as 800 MHz or 1.5 GHz, for example, for information transmission. As electronic parts for amplifying such high-frequency signals with low noise or with high efficiency, heretofore used are MESFET (metal semiconductor FET) using a III-V compound semiconductor, particularly GaAs, as its substrate, or MMIC (monolithic microwave IC) using the GaAs MESFET as its building block.
In GaAs MESFET, because of the advantages of its substrate material, namely, (1) electron mobility being high, (2) dielectric constant of the substrate being larger than that of SiO.sub.2 by several times, (3) a substrate with a specific resistance as high as several M.OMEGA.cm, and so on, a high transmission gain and a low noise factor could be obtained under a low source voltage even in those high frequency bands.
There are different types of GaAs MESFETs, depending on the method for making channel layers, namely, those made by ion-implanting an n-type impurity such as Si into a GaAs substrate (hereinafter abbreviated "ion-implanted MESFET") and those in which the channel layer is made by epitaxial growth (hereinafter abbreviated "epi-MESFET"). Central parts of cross-sectional structures of an ion-implanted MESFET and an epi-MESFET, as using semi-insulating GaAs substrates, are shown in FIG. 1 and FIG. 2, respectively.
In the ion-implanted MESFET shown in FIG. 1, after an n-type impurity and a p-type impurity are ion-implanted into a semi-insulating GaAs substrate 101, annealing is conducted for activating the impurities to thereby make an n-type channel layer 102 and a p-type buried layer 103 in the semi-insulating GaAs substrate 101. The p-type buried layer 103 functions to form a potential barrier against the majority carrier in the n-type channel layer and to suppress the substrate leak current caused by an electric field of the drain depletion layer. Subsequently, a source electrode 104 and a drain electrode 105 are made to get into ohmic contact with the n-type channel layer 102. Finally, a gate electrode 106 is made on a part of the n-type channel layer 102 between the source electrode 104 and the drain electrode 105 to form a Schottky junction 107. Thus, the basic structure of MESFET is completed. Numeral 108 denotes the depletion layer formed along the Schottky junction 107.
Usually, in addition to these steps of the process, some other steps are executed, for making a source region and a drain region by high-concentrated impurity implantation for the purpose of reducing ohmic contact resistance of the source electrode 104 and the drain electrode 105, and for etching the substrate surface in the gate region for the purpose of improving the resistance to voltage of the drain or controlling the threshold voltage (recess process). However, explanation thereof is omitted here.
On the other hand, in the epi-MESFET shown in FIG. 2, a barrier layer 202 and an n-type cannel layer 203 are sequentially epitaxially grown on a semi-insulating GaAs substrate 201. The barrier layer 202 corresponds to the p-type buried layer 103 in the ion-implanted MESFET shown in FIG. 1. In some cases, the barrier layer 202 is made of the same material as the n-type channel layer 203 similarly to the ion-implanted MESFET, and in other cases, it is made of a semiconductor material having a larger band gap than that of the n-type channel layer 203. After that, a source electrode 204 and a drain electrode 205 in ohmic contact with the n-type channel layer 203 are made. Finally, a gate electrode 206 is made on a part of the n-type channel layer 203 between the source electrode 204 and the drain electrode 205 to form a Schottky junction 207. Thus, the basic structure of MESFET is completed. Numeral 208 denotes the depletion layer formed along the Schottky junction 207.
Although the ion-implanted MESFET can be made at a lower cost than the epi-MESFET, the degree of freedom in designing the channel structure is small. This is because the concentration profile of the channel impurity is restricted by a certain distribution typical to the ion implantation.
On the other hand, in the epi-MESFET, relatively free channel impurity concentration profiles can be realized by controlling the flow rate of the doping source material gas upon epitaxial growth. Therefore, for making channel layers by epitaxial growth, there were used so-called low-high doping capable of making a retrograde concentration profile in which the impurity concentration progressively increases as getting deeper, or making a discontinuously changing impurity concentration, such as forming a low-concentrated layer on a high-concentrated layer, planar doping for making a very thin doping layer, and so on (for example, IEEE ED-25, p.600(1978)).
However, for making MMIC integrating RF switches, power amplifiers, etc. by using the above-introduced MESFET, two kinds of power sources, positive and negative, are usually required as its power source. This is presumably because a low ON resistance and an enough saturation drain current required in MMIC cannot be readily obtained with a positive power source alone.
On the other hand, Japanese Patent Laid-Open Publication No. hei 4-84440 discloses a technique for fabricating a p.sup.+ -type gate diffusion layer, i.e., a gate region, by sequentially epitaxially growing an n-type GaAs epitaxial layer as a channel layer and an n.sup.+ -type GaAs epitaxial layer as a source and a drain on a semi-insulating GaAs substrate via a buffer layer, then making a silicon nitride film as a diffusion mask thereon, and diffusing a p-type impurity like Zn or Mg, for example, into the n-type GaAs epitaxial layer through the n.sup.+ -type GaAs epitaxial layer. This technique, however, cannot make the gate electrode in self alignment with the gate diffusion layer because it makes the ohmic electrode for the gate diffusion layer, i.e., the gate electrode, after making the gate diffusion layer by using the diffusion mask, and then removing the diffusion mask. As a result, the width of the gate diffusion layer must be larger than the width of the gate electrode, and this means that the gate length cannot be made shorter than the alignment accuracy of lithography. That is, with this technique, decrease of the gate length and higher operation thereby cannot be expected.